Steven G. Abstract The electronic structure of vacuum-semiconductor and metal-semiconductor interfaces has been studied using a method involving self-consistent pseudopotentials. Fingerprint Surface states. Semiconductor materials.
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Charge density. Electronic structure. Here, you will first relax the three interface structures as bulk configurations i. Then use the Center tool to center the configurations along C only. Finally, use the Hydrogen passivation tool to passivate the dangling bonds on the Si surface farthest from the interface. Note that this may add H atoms to the left of the silicon part as well as to the right. Any hydrogen placed in the interface should obviously be removed.
You are now ready to relax each configuration. Use the same calculator settings as for the Ag electrode relaxation, and use the following parameters in the OptimizeGeometry block:. Finally, add also the TotalEnergy analysis block to the scripts. Run the calculations. They are a bit demanding and require roughly 20 hours on a core node. You should find that the structure where the silicon connects to the Ag hollow sites is the most stable it has the most negative total energy, see below.
In the following, only this configuration will be used. This final device relaxation should use the same calculator and geometry optimization parameters as for the bulk relaxation above, except that the k-point sampling along C must be increased to use a 6x3x grid. The calculation takes about 2 hours on 16 cores. We use the TB09 meta-GGA functional [cTB09] to calculate the projected local density of states and transmission spectrum of the device.
In order to obtain an accurate description of the Si side of the interface, the TB09 c-parameter is fitted to match the silicon band gap. The calculations are quite fast and can be run locally. You should obtain a band gap of 1. Do similar calculations with fixed c-values around 1.
Use the Editor to insert the loop:. Remember that the Bandstructure block should be included in the loop, just below the Calculator section. Fit the c-value to the experimental band gap of 1. It needs three input parameters; a list of the used c-values tb09 , the name of the. You are now ready to dope the silicon part of the device.
It is important to consider the length of the depletion layer in your device: The device needs to be longer than the screening length of the semiconductor so that the potential on the silicon side at the boundary with the silicon electrode resembles that of bulk silicon. This can be done by studying the convergence of the Hartree potential with respect to the length of the silicon central region. You only need to converge the length of the silicon side of the interface, since the metal have a much shorter screening length.
The 6 atomic layers of Ag will be sufficient. Increase the length of the silicon part of the central region by using the Central Region Size plugin. Use a calculator with the same parameters as for the device relaxation, and add the HartreeDifferencePotential block. Note that the calculations become increasingly difficult to converge as the length is increased.
The calculation for the largest device requires around 13 hours on 16 cores. When all calculations have finished and the results appear on the LabFloor , you can plot the potentials along the Z-direction using the 1D projector analysis tool. The potential should be flat in the vicinity of the boundary with the silicon electrode.
The wiggles of the potential can make it hard to see if it has converged to the electrode value. Use the script hdp.
Electronic structure of metal-semiconductor contacts - Semantic Scholar
The script needs to be edited, as it contains some input parameters specific to the interface structure:. Once you have edited these parameters, run the script once for each of the the. Modify the following input parameters:. Note that the depletion layer length could change slightly with the bias. You now have the final device. The kink at the interface border in the plot above is due to the averaging procedure, where Gaussians of different widths are matched at the Ag—Si border.
Use the Analysis from File block in the Scripter to load the saved device configuration and the converged calculator attached to it. Save the results in the. The calculation will take around 7 hours on a core node with 64 GB of memory.
Chapter 3: Metal-Semiconductor Junctions
It requires the. In this plot, you can easily see the metal-induced gap states to the right of the interface border. Moreover, the averaged potential nicely follows the conduction band minimum, both at the interface and far from it. The plotting script returns this value together with the plot.
You will get a barrier of around 0. You will need this value later on for analyzing the spectral current. We will investigate the I—V characteristics next.
Electronic Structure Metal-semiconductor Contacts
Choose the following settings for the analysis:. The calculation will require around 15 hours on 16 cores. You can use the IV-Plot plugin to plot the calculated current vs. The script requires a. The interface shows Schottky diode-like behavior, with a large increase in the current at forward bias but a rather small increase at reverse bias.
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